Parallel algorithms for logic synthesis using the MIS approach

Combinational logic synthesis is a very zmportant but compututionally expensive phase of VLSI system design. Parallel processing offers an attructive solution to reduce this design cycle time. In this paper; we describe ProperMIS, a portable parallel algorithm for logic synthesis based on the MIS multi-level logic synthesis system. As part of this work, we have developed novel parallel algorithms for the d@rent logic transformations of the MIS system. Our algorithm uses an asynchronous messagedriven computing modei with no synchronizing barriers separating phases of parallel computation. The algorithm is portable aclnss a wide van’ety ofparallel architectures, and is built around a well-defied sequential algorithm interface, so that we can beneJi! from future expansion oj’the sequentral algorithm. We present results on several MCNC and ISCAS benchmark circuits for a varlc’ty of shared memory and distributed processing architectures. Our implementation produces speedups oj‘lzn average o.f 4 on 8 processors.